This invention relates to semiconductor devices, and more particularly, to an LDMOS (lateral double-diffused metal oxide semiconductor) deice having an oversized DWELL to compensate misalignment during is manufacture.
DMOS devices are xe2x80x9cdouble diffusedxe2x80x9d MOS (metal oxide semiconductor) transistor devices. A DMOS device is characterized by a source region and a backgate region, which are diffused at the same time. The transistor channel is formed by the difference in the two diffusions, rather than by separate implantation. DMOS devices have the advantage of decreasing the length of the channel, thereby providing low-power dissipation and high-speed capability.
DMOS devices may have either lateral or vertical configurations. A DMOS device having a lateral configuration (referred to herein as an LDMOS), has its source and drain at the surface of the semiconductor wafer. Thus, the current is lateral.
In general, an LDMOS is designed for a desired breakdown voltage (BV) and a low specific on-resistance (Rsp). In general, the design goal is to keep Rsp as low as possible for a given voltage range. The Rsp is a widely used figure of merit, and is the product of the on- resistance, Ron, and the area of the transistor cell, Area:
Rsp=Ron * Area
The source to drain spacing is directly related to Ron, with a larger spacing resulting in larger Ron.
It is desirable to have an LDMOS that is rated for multiple voltage, i.e., 16-60 volts. However, it is difficult to provide such a device having both the desired voltage characteristic and low Rsp.
One aspect of the invention is an LDMOS device having an oversized DWELL. Various embodiments of the invention provide high, medium, and low voltages LDMOS devices, and high-side and low-side variations.
For the high voltage, low-side embodiment, the device is formed on a p-type semiconductor layer. A deep Nwell is formed in the semiconductor layer and contains the device. A Dwell is formed in the Nwell. This Dwell has a p-type region and a shallower n-type region. An n+ source region is formed in the Dwell and an n+ drain region is formed in the Nwell, with the source region and the drain region being spaced apart such that a channel is formed between them. A p+ backgate region is formed in the Dwell adjacent the source region such that the source region separates the backgate region and the channel. A p+ anode region is formed between the drain region and the channel region. A gate oxide layer is formed over the channel and a gate is formed over at least part of the source region and the channel. The Dwell is oversized in the sense that it is implanted past the source edge of the gate. As a result, not only does its p-type region diffuse under the gate, but also its shallow n-type region diffuses well past the source edge of the gate.
An advantage of the invention is that the LDMOS may be manufactured using an 0.72 xcexcm (micron) BiCMOS fabrication process with a photo-aligned Dwell. By using an oversized Dwell, a reduction in size and junction depth of the source and drain regions, with the accompanying reduction in junction depth of the n-type region of the Dwell, can be accomplished without Dwell misalignment problems and other adverse effects. The LDMOS has excellent BV vs Rsp characteristics as well as reduced die area.